Jitter – An Introduction

Serial data systems play an increasingly important role whenever volumes of data are processed or transported. Jitter is a key concern for engineers developing high speed components such as transmitters, receivers and data channels. Serial high speed communication systems need to operate within very tight margins; with data provided extremely fast and with an exceptionally low probability of errors. The challenge for developers is to create high speed systems at very low cost so products can be competitively marketed.

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WHITEPAPER Jitter – An Introduction By Wolfgang Damm, Product Management Director, Wireless Telecom Group Abstract: Serial data systems play an increasingly important role whenever volumes of data are processed or transported. Jitter is a key concern for engin- eers developing high speed components such as transmitters, receivers and data channels. Serial high speed communication systems need to operate within very tight margins; with data provided extremely fast and with an exceptionally low probability of errors. The challenge for developers is to create high speed systems at very low cost so products can be competitively marketed. Discussing the subject matter of jitter completely would exceed the scale of this paper. Instead, it provides a general introduction to jitter, causes and methods of jitter measurements, specifically BER and the eye diagram. It will also talk about examples of standards concerning jitter-tolerance-measurements for serial high speed components and will take a closer look at the test setup for a serial high speed PCI express receiver. What is Jitter? “Jitter” is a term used in the digital domain, even if causes and resulting effects are very much of analog nature. Binary information is transmitted as bits in a data stream of random ones and zeros. In an ideal world these bits would be available strictly at a certain time and be present for an exactly predetermined period. Fur- thermore, they would have uniform high and low levels. Unfortunately, the real world scenario is far from ideal. Designers have to overcome a variety of factors that influence and the transmitted data signal quality and happen to be a source of jitter. Jitter is commonly recognized as a high frequency quantity. Jitter-like be- Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 1 of 7 havior at frequencies below 10 Hz is called “wander” and “drift” at even lower fre- quencies. Though they are a concern in large-scale synchronous systems, wander and drift play a negligible role in asynchronous systems because they are easily tracked by clock data recovery units. Asynchronous systems do utilize independent reference clocks for transmitters and receivers. The needed clock frequency in a serial receiver is extracted from the incoming data stream, where bit transitions are utilized to synchronize the phase locked looped VCO of a clock data recovery unit (CDR). Phase & Amplitude Jitter Timing variations relative to the ideal transition time are called phase jitter (Fig. 1 top). Signal level variations also occur in digital systems; are called amplitude jitter (Fig. 1 bottom). Because of finite signal transition times, state level vari- ations have an impact on the sys- tems binary state determination. De- pending on its originating level just before transition, the slope of the signal reaches the threshold determ- ining the actual bit state somewhat sooner or later. This again has an effect on the “1” or “0” decision peri- od available to the system. Since it is always dependent on the techno- logy standard, there is no universal definition of jitter. The International Telecommunication Union (ITU-I) defines Jitter as: The short-term variation of the significant instants of a digital signal from their ideal positions in time. Jitter can be bounded or unbounded. The former is related in frequency and magnitude to system events; therefore, bounded jitter is deterministic. This means disabling the source will stop related bounded jitter too. Bounded jitter al- ways has a limited magnitude. An example would be Inter Symbol Interference (ISI): signal transitions cause interference to the neighboring channels, but if the Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 2 of 7 Figure 1. Phase and amplitude jitter influence digital systems and can cause bit errors. originating data lines are inactive no interfer- ence occurs. Because of the finite energy of originating events, res- ulting jitter is also finite and always attenuated. Unbounded jitter does not depend on events. System components or external influences can cause it. Most promin- ent is Random Jitter (RJ), which is caused by white noise prevalent in all active and passive components. Amplifiers and line drivers multiply the energy of noise. By its nature, energy distribution of white noise is Gaussian, so RJ can be described by the probability density function: PDF RJ (x) = Equation 1 where x is the independent value and σ (sigma) the RMS value and μ (mu) the mean of the distribution. Jitter is defined as deviation from the ideal state, which means it has positive and negative variations relative to the ideal state. For this reason μ in jitter analysis is always 0 and can be omitted. Equation 1 indicates that independently of how large x may become, the probability of certain jitter causing events may become very small, but it will never reach the x-axis. Due to its wide frequency spectrum white noise is very difficult to suppress or attenuate without impacting the actual signal. System Jitter is caused by a variety of sources, and is either random or determin- istic. The latter means that its causes are clearly linked to system events. As de- scribed above, such causes could for example be interference with neighboring channels during level transitions or insufficiently filtered switching pulses that are carried over from a switching power supply onto the Vcc network. Table 1 provides a full description of jitter causes. Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 3 of 7 ISI Intersymbol Interference DCD Duty Cycle Distortion DDJ Data Dependent Jitter PJ Periodic Jitter DJ Deterministic Jitter TJ Total Jitter RJ Random Jitter ECJ Echo Jitter Figure 2. The jitter tree shows types of jitter that can influ- ence high speed serial data systems. Jitter Term Description TJ Total Jitter The summation (or convolution) of deterministic and random jitter. Total jitter is the peak to peak value obtained. TJ = DJ + n × RJ where n = number of standard deviations corresponding to the required BER. RJ Random Jitter The principal source is Gaussian (white) noise within system compon- ents. It interacts with the slew rate of signals and produces timing er- rors at the switching points. DJ Deterministic Jitter Jitter with non-Gaussian probability density function. It is always bounded in amplitude and with specific causes. Sources are imperfec- tions of devices, crosstalk, EMI, grounding problems. PJ Periodic Jitter Also called Sinusoidal Jitter due to its sinusoidal form. The source is usually interference form signals related to the data pattern, ground bounce or power supply variations. DDJ Data dependent Jitter Consists of Inter Symbol interference (ISI), Duty Cycle distortion (DCD), and Echo Jitter (ECJ). Timing errors vary with data pattern. Primary source are component and system bandwidth limitations. Higher frequency signals have less time to settle than lower frequency ones. This leads to changes in the start conditions for transitions at dif- ferent frequencies and produces timing errors dependent on the data pattern being applied. ISI Inter Symbol Interfer- ence Inter symbol interference is the most common form of DDJ. It is usually caused by bandwidth limitations of transmission lines. It affects single bits surrounded by the bit of the opposite state. DCD Duty Cycle Distortion Duty Cycle Distortion Jitter is caused when certain bit states have dif- ferent durations. “1” is always longer than “0” or vice versa. Caused by bias setting, and insufficient VCC supply of a component. ECJ Echo Jitter Echo Jitter is caused by component/line mismatch, it depends on the data pattern. Line length influence the magnitude of ECJ as well. Table 1. Jitter types that can influence serial data systems. Measuring Jitter: Eye Diagram & BER How to measure high speed data streams and analyze integrity of the data streams transmitted or received? The prevalent way to conduct this measure- ment is to determine the Bit Error Rate (BER). A known (pseudo-) random bit stream is injected into the device under test (DUT). The output of the DUT is compared against the known data pattern and possible bit errors are counted: BER = NErr / NBits Equation 2 Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 4 of 7 where BER is the measured bit error rate, NErr the number of error bits and NBits the entire number of compared bits. This requires very sophisticated measure- ment equipment that allows the comparison of each bit’s amplitude and transition timing and offers capabilities to adjust the signal propagation delay that is en- tailed with the DUT. The ideal condition serves as reference for jitter related measurements and is called unit interval (UI): 1 UI = time period of 1 symbol Transition time and (differential) amplitude influence the outcome of measure- ments and determine the binary value of a particular bit. Special BERT testers or oscilloscopes represent the entire data stream through an eye diagram. All measured bits are displayed at the same time. While the measurement techno- logy has to be quite sophisticated due to very high data speeds and relatively low signal levels, the principle of creating an eye diagram is quite simple (Fig. 3). In Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 5 of 7 A B C D Figure 3. The eye diagram presents the behavior of a very long data stream in a 2UI window. The whole data stream is folded into the window. The eye diagram allows determination of a signal’s compliance with requirements defined by the technology standards. Eye diagrams C and D are stretched in the x-axis by a factor of 2.5 for better resolution. our example, a bit stream (A) is broken in equal increments: I1 to I11 (B), each the size of one bit period, which means per definition 1 UI. To allow detailed analysis of the most important signal parts – the transitions – increments of 2 UI; 0.5 UI pre-transition, 1UI bit sample and 0.5 UI post-transition are recorded and overlaid in a 2 UI wide window. The result is the eye diagram as shown in (Fig. 3 C). The ideal shape of a data bit would match exactly one unit interval (UI) in both, time and amplitude. Furthermore, under ideal conditions the tolerance margin would be nearly 1UI (–0.5 UI to +0.5 UI relative to the bit center), to recognize signal states properly. The cumulative influence of jitter sources alters signal amp- litude and transition timing which reduces the tolerance margin significantly. Com- pliance opening as depicted in fig. 2 D tells exactly how much signal transitions and levels are allowed to vary from the ideal state before they cause a bit error. Technology standards provide exact descriptions of test setups and measurement margins necessary for meaningful pass / fail decisions. Table 2 shows an excerpt of these require- ments for PCIe 2.0, 10Gb Ethernet and SATA II. Some formats allow for more than 50% margin while others are far stricter. The reader may consult the actual technology standards for more comprehensive information. Figure 4 shows the simplified test setup for a PCIe 2.0 jitter compliance test of a serial receiver (DUT). Purpose of this test setup is to expose the DUT to signal conditions that are defined by the standard. Once the DUT passes the compliance test, it is en- sured that the hardware will work well with other components that also passed the test. A pattern generator provides a known data stream to the DUT. For syn- chronous systems, both, DUT and pattern generator are clocked with the same precision clock. Output data of the DUT is compared with the pattern generator for BER analysis. DUT stressing is achieved by varying the signal’s amplitude, through different data patterns and generating different data speeds, as seen at the bottom of the pattern generator. The original data stream is additionally mod- ulated in different ways. A variable signal generator with a range from 1.5 to 100 MHz generates PJ conditions, another generator, fixed at 33kHz, serves as spread spectrum clocking simulation. Signal’s transition timing is altered through a phase generator and a Gaussian white noise generator that injects RJ with Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 6 of 7 Table 2. Example (excerpt) of measurement require- ments for PCIe 2.0, 10 GBE, and SATA II spectral distribution. Finally ISI is generated through special crosstalk lines at the output of the pattern generator. Conclusion This paper introduced different types of jitter: random jitter (RJ), deterministic jit- ter (DJ) and deterministic jitter’s most important sub-classes. Also discussed were the influence of jitter on the signal integrity of high-speed serial data sys- tems and methods of measurement (BER, eye diagram). Wireless Telecom Group Whitepaper: Jitter – An Introduction www.wtcom.com, Phone: +1-973-386-9696 Page 7 of 7 Figure 4. Jitter test setup (simplified) for PCIe 2.0 conformance testing