1
Introduction
The issue of tombstoning rose to prominence because,
while components and assemblies have become much
smaller over time, overall assembly processes have
remained much the same. As components become
smaller, so can your process windows.
There was a time when a Type 2 solder paste and
chemically etched stencil were acceptable for almost all
assemblies. Throughout the 1990s, Type 3 solder paste
and laser cut stencils became the norm. For those using
micro-components today, a Type 4 solder paste and
an electroformed stencil can be a prerequisite to highly
consistent stencil printing. Likewise, equipment that
can place components within +/- 50-100 microns (while
suitable in its day) is no longer acceptable when placing
0201s or even 01005s. Ovens too have become more
capable as well.
Tombstoned component
Why does a component tombstone?
As the flux and solder alloy liquefy and wet to each side
of a component, they apply small amounts of torque
through surface tension. The torque applied by the
surface tension of liquid flux and solder has traditionally
been a fringe benefit, helping to center misaligned chip
components.
However, this friend has become a foe in modern electronics
assembly. Tombstoning is caused by minute differences
in wetting force from one side of a chip component to
the other. When there is a sufficient imbalance in torque,
relative to the mass of the component, the component is
tipped upright (tombstoned), consigning the product to
either scrap or rework.
Chip components have gotten much smaller over the years
with many weighing in the milligrams. The same torque that
once helped alignment now has the power to tombstone
components. The only way to completely eliminate the
tombstoning effect is to tighten your process variables.
There are many process variables that actively contribute
to tombstoning. These include, but are not limited to, trace/
board design, pad design, component and board oxidation,
solder paste, stencil design, print process, placement
process, and reflow process. Appropriate modification
of one or more of these process variables will reduce or
eliminate tombstoning.
Key tombstoning variables
Trace/Board Design – When board designers are laying
out a circuit board, manufacturability considerations
are often unknown or ignored. Having established that
wetting force imbalance causes tombstoning, one of
the primary causes for imbalance is the difference in
temperature and, correspondingly, the difference in time
of reflow between the two pads the chip sits on.
Pad 2 Pad 1
Example: Pad 1 is connected to a wide trace, ground plane, or other
heat sinking element. Pad 2 is connected to a thinner trace or less
massive circuitry element. Pad 2 will often be hotter than Pad 1 and
reflow before Pad 1. This temperature difference results in a reflow
timing difference. When Pad 2 wets first, the wetting force from Pad
2 may be enough to overcome the force from Pad 1 resulting in a
tombstoned component.
Tombstone Troubleshooting
John Vivari, Nordson EFD
Figure 1
Paste has not
fully wet
Paste wets,
producing
torque,
which lifts
component
2
Pad Design – Mechanical advantage also plays a role in
both tombstoning and skewing for the same reasons. The
larger the pad relative to the size of the component, the
longer the “lever” that the liquid flux and solder can apply.
When a pad is too wide, imbalance in force between side
fillets will skew the component. When a pad is too long it
increases mechanical advantage applied by the toe fillet,
making it easier to tombstone the component.
Chip component pads should be no larger than necessary
to meet mechanical and inspection requirements. In some
cases, visual inspection requirements for fillet height will
prevent the successful elimination of tombstoning due to
restrictions on other aspects of the process.
Component and Board Oxidation – Oxidation on either
pad or component surfaces will cause slight delays in
wetting. The difference in wetting time from one pad to
the other can cause tombstoning. High quality boards and
components along with proper storage practices will help
to eliminate this factor.
Component Geometry – Capacitors, inductors, and
other “thick” chip components are statistically more
likely to tombstone than resistors and other “thin” chip
components. The risk of tombstoning is larger for the
same reason as for oversize pads. The distance that
the flux and solder wet up the termination adds to
mechanical advantage.
Component size and mass also play a key role. The lighter
the component, the less force it takes to tombstone.
A process that is tombstone free with 0603 components may
be unsuited to 0402 components. As newer, smaller chips
are introduced into your production process, incremental
changes may be required to deal with the new challenge.
Sample chip components (left to right): 0805, 0603, 0402, 0201, 01005
Solder Paste – Solder paste is actually a mixture
of two independent materials: flux and alloy. In rare
circumstances, particularly bad flux formulations do not
provide sufficient tack just prior to and during reflow.
Side-by-side comparisons of pastes are required to
identify differences in performance.
With regards to alloy, it turns out that there is a difference
in performance between eutectic and non-eutectic
alloys. Eutectic alloy changes state from solid to liquid all
at once at a single temperature, developing full surface
tension suddenly. Non-eutectic alloys change state
gradually over a temperature range, developing surface
tension over a longer time period, applying surface
tension in proportion.
Non-eutectic alloys such as Sn62/Pb36/Ag2 and Sn96/
Ag3.0/Cu0.5 have correspondingly lower incidence of
tombstoning than Sn63/Pb37 and other eutectic alloys.
The larger the melting range, the lower the probability of
tombstoning.
Alloy Solidus (° C) Liquidus (° C)
Sn42 Bi58 -E- 138
Sn43 Pb43 Bi14 144 163
Sn62 Pb36 Ag2.0 179 189
Sn63 Pb37 -E- 183
Sn60 Pb40 183 191
Sn96.5 Ag3.0 Cu0.5 217 219
Sn96.3 Ag3.7 -E- 221
Sn100 MP 232
Sn95 Sb5 232 240
Sn95 Ag5 221 245
Sn89 Sb10.5 Cu0.5 242 262
Sn10 Pb88 Ag2.0 268 290
Sn5 Pb92.5 Ag2.5 287 296
Sn10 Pb90 275 302
Sn5 Pb95 308 312
-E-: Eutectic MP: Melting point : Lead free
Stencil Design – Stencil design has two elements:
aperture design and stencil technology choice. Stencil
aperture design determines two things: paste volume
printed and paste location. A good stencil design will
place only as much solder paste as is required. Too much
paste will produce too tall a fillet and greater torque during
liquefaction of the solder. A good design also places the
solder in a location that ensures appropriate component-
to-paste overlap. With too little overlap, there may be
inadequate adhesion on the pad that reflows second. With
too much overlap, solder beads/balls show up on the side
of chip components.
Stencil technology defines the expected paste release
characteristics. In order of increasing paste release
performance there are chemically etched stencils, laser
cut stencils, and electroformed stencils. Electropolishing
and secondary plating of chemically etched and laser cut
stencils have been proven to improve their paste release
performance.
0805 0603 0402 0201 01005
US Quarter shown for scale
3
Print Process – One factor that has been shown to
dramatically decrease tombstoning is the quality of print.
With more uniform deposits, adhesion is more even from
pad to pad. For 0201 apertures and others similar in size,
Type 4 and Type 5 solder pastes have been proven to
significantly improve print quality. Print settings should be
optimized for maximum print definition and uniformity.
Placement Process – If the component is placed more
to one side or another, it will allow more surface tension to
be applied to that side, and the component can stand up.
If the component is not placed with sufficient pressure, it
will begin to tip as wetting occurs, and if it is pushed too
deeply into the paste, the paste will be displaced, and
(again) uneven wetting may occur.
Reflow Process – The reflow process is probably the
most significant contributor to tombstoning. When a
board design with tombstone-friendly features is sent
through the oven, how the board is heated can make a
tombstone problem either better or worse. To minimize
tombstoning, the goal is to ramp temperature such that
the solder alloy liquidus is achieved uniformly for all pairs
of pads on the board. This means that the whole board
should be brought to a temperature just below liquidus, and
then slowly ramped up to reflow. By keeping wetting forces
equal on both sides of a chip component, it is less likely to
tombstone. For most products, a ramp rate of around 1° C
per second is adequate insurance against reflow-induced
tombstoning. More difficult products may require slower
ramp rates with some as low as 0.33° C per second.
Tombstone Optimized Profile
Conclusion
Every instance of tombstone components can be traced
back to one or more of the variables discussed. If you
do have tombstone components on an assembly, time
spent on root cause analysis can quickly narrow down
which variables are contributing to your problem. If one
or two variables are difficult to change, sometimes the
remaining variables can be manipulated to overcome
weaknesses in design or process elements. If the
tombstone problem resists your efforts, contact your
solder paste supplier for assistance.
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please request samples. Simply go to
www.nordsonefd.com/SolderSampleRequest.
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