California Inventor Develops Cache-Miss Performance Improvement Method

ALEXANDRIA, Va., May 9 -- Brian D. Emberling of San Mateo, Calif., has developed a method for improving cache-miss performance.

According to the U.S. Patent & Trademark Office: "A cache memory with improved cache-miss performance is implemented by providing cache-miss data from system memory directly to its requester. One embodiment of the invention operates as a texture cache in a graphics system. The graphics system comprises a system memory that stores texture data, coupled to a texture cache memory, which is coupled to at least one requester. The texture cache memory is divided into a cache tags unit and a data cache unit. The data cache unit is configured to receive at least two cache address inputs, and has at least two data output ports each coupled to a respective first input of a respective multiplexer."

An abstract of the invention, released by the Patent Office, said: "A respective second input of each multiplexer is configured to receive cache-miss data from the system memory. The select input of each multiplexer is configured to receive a respective hit/miss indicator signal associated with the respective cache address input. In case of a cache-miss, cache-miss data from system memory bypasses the data cache unit and is output directly. The cache-miss data is then written into the data cache unit during a subsequent clock cycle."

The inventor was issued U.S. Patent No. 7,360,020 on April 15.

The patent has been assigned to Sun Microsystems Inc., Santa Clara, Calif.

The original application was filed on March 31, 2003, and is available at: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7,360,020.PN.&OS=PN/7,360,020&RS=PN/7,360,020.

For more information about US Fed News federal patent awards please contact: Myron Struck, Managing Editor/US Bureau, US Fed News, Direct: 703/866-4708, Cell: 703/304-1897, Myron@targetednews.com