Massachusetts Inventor Develops Multithreaded Processor Estimation Apparatus

ALEXANDRIA, Va., May 9 -- Alexandra Fedorova of Lincoln, Mass., has developed a method for estimating a multithreaded processor.

According to the U.S. Patent & Trademark Office: "An estimate is calculated of the throughput of a multi-threaded processor having N threads based on measured miss rates of a cache memory associated with the processor by calculating, based on the cache miss rates a probability that the processor is in a state with one thread running, a probability that the processor is in a state with two threads are running and continuing to a probability that the processor is in a state with N threads running, multiplying each probability by a measured throughput of the processor when it is in the corresponding state and summing the resulting products. This estimate may also be corrected for bus delays in transferring information between the cache memory and main memory. The estimate can be used for thread scheduling in a multiprocessor system."

The inventor was issued U.S. Patent No. 7,363,450 on April 22.

The patent has been assigned to Sun Microsystems Inc., Santa Clara, Calif.

The original application was filed on June 1, 2005, and is available at: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7,363,450.PN.&OS=PN/7,363,450&RS=PN/7,363,450.

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